IOLTS 2010 - Call for Participation

CALL FOR PARTICIPATION

Scope -- Key Dates -- Venue -- Workshop Registration -- Advance Program -- More Information -- Committees

Scope

Issues related to on-line testing are increasingly important in modern electronic systems. In particular, the huge complexity of electronic systems has led to growth in reliability needs in several application domains as well as pressure for low cost products. There is a corresponding increasing demand for cost-effective on-line testing techniques. These needs have increased dramatically with the introduction of very deep submicron and nanometer technologies which adversely impact noise margins, process, voltage and temperature variations, aging and wearout and make integrating on-line testing and fault tolerance mandatory in many modern ICs. The International On-Line Testing Symposium (IOLTS) is an established forum for presenting novel ideas and experimental data on these areas. The symposium also emphasizes on-line testing in the continuous operation of large applications such as wired, cellular and satellite telecommunication, as well as in secure chips. The Symposium is sponsored by the IEEE Computer Society Test Technology Technical Council and organized by TIMA Laboratory, University of Athens, and University of Piraeus.

Key Dates

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Advance Registration Deadline: May 25, 2010!
Hotel Reservations Deadline: June 4, 2010

The Venue

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IOLTS 2010 will be held in Corfu island which was not named the “Emerald Island” without reason. Corfu's natural beauty hides itself beneath a cloak of emerald green trees, with a mountainous skyline plunging into the bluest of blue waters. Elegant architecture, sun drenched beaches, enchanting night life, and fine cuisine all play their part in attracting visitors from all over the world.

Registration & Reservations

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To register for the symposium go to: http://tima.imag.fr/conferences/iolts/iolts10/registration.html

To make your hotel reservations go to: http://tima.imag.fr/conferences/iolts/iolts10/reservation.html

Advance Program

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Monday -- day -- day

July 5, 2010 (Monday)

7:30 AM - 9:00 AM SYMPOSIUM REGISTRATION

9:00 AM - 10:00 AM	OPENING SESSION
09:00 - 09:15	Welcome Message M.Nicolaidis (TIMA Lab), A.Paschalis (U Athens), General Chairs D.Gizopoulos (U Piraeus), A.Chatterjee (Georgia Tech), Program Chairs
09:15 - 10:00	Keynote: Industrial Impacts of SER on Today's Consumer Electronic Arenas Philippe Roche, ST Microelectronics

10:00 AM - 10:15 AM BREAK

10:15 AM - 11:35 AM	Session 1 - Degradation Modeling and Monitoring
1.1	A Self-Consistent Model to Estimate NBTI Degradation and a Comprehensive On-Line System Lifetime Enhancement Technique G.Karakonstantis, C.Augustine, K.Roy (Purdue University)
1.2	Predictive Error Detection by On-line Aging Monitoring J.Vazquez, V.Champac, A.Ziesemer Jr., R.Reis, J.Semiao, I.Teixeira, M.Santos, J.P.Teixeira (INAOE, UFRGS, U. Algarve, IST/INESC-ID, Lisboa Technical U.)
1.3	Temperature Dependence of NBTI Induced Delay S.Khan, S.Hamdioui (Delft U.)
1.4	Aging Test Strategy and Adaptive Test Scheduling for SoC Failure Prediction H.Yi, T.Yoneda, M.Inoue, Y.Sato, S.Kajihara, H.Fujiwara (Nara Institute of Science and Technology, Kyushu Institute of Technology)

11:35 AM - 11:50 AM COFFEE BREAK

11:50 AM - 12:50 PM	Session 2 - Transients Analysis and Evaluation
2.1	Analysis of Root Causes of Alpha Sensitivity Variations on Microprocessors Manufactured using Different Cell Layouts P.Rech, M.Grosso, F.Melchiori, D.Loparco, D.Appello, L.Dilillo, A.Paccagnella, M.Sonza Reorda (LIRMM, Politecnico Di Torino, ST Microelectronics, U. Padova)
2.2	Evaluating Transient-Fault Effects on Traditional Implementations of the C-element R.Possamai Bastos, G.Sicard, F.Kastensmidt, M.Renaudin, R.Reis (UFRGS, TIMA, Tiempo, and Instituto de Informatica)
2.3	Probabilistic Methods for the SET Impact in Combinational Logic S.Gangadhar, S.Tragoudas (Southern Illinois U Carbondale)

12:50 PM - 2:00 PM LUNCH

2:00 PM - 3:00 PM	Session 3 - Multicore/Manycore On-Line Testing
3.1	Analysis of On-Line Self-Testing Policies for Real-Time Embedded Multiprocessors in DSM Technologies O.Heron, J.Guilhemsang, N.Ventroux, A.Giulieri (Institute für Teschniche Informatik, CEA LIST, and LEAT)
3.2	Distributed Online Software Monitoring of Manycore Architectures E.Faure, M.Benabdendi (TIMA Lab), F.Pêcheux (LIP6, U Pierre and Marie Curie, TIMA Lab)
3.3	SBST for On-Line Detection of Hard Faults in Multiprocessor Applications Under Energy Constraints A.Merentitis, D.Margaris, N.Kranitis, A.Paschalis, D.Gizopoulos (U Athens and U Piraeus)

3:00 PM - 3:15 PM BREAK

3:15 PM - 4:15 PM	Session 4 - Analog and Mixed-Signal Circuit Testing
4.1	An Analog VLSI Implementation of a Multilayer Perceptron and its Application towards Built-In Self-Test in Analog Circuits D.Maliuk, H.Stratigopoulos, Y.Makris (Yale U., TIMA Lab)
4.2	Built-In Performance Monitoring of Mixed-Signal/RF Front Ends Using Real-Time Parameter Estimation S.Kumar Devarakond, V.Natarajan, S.Sen, A.Banerjee, A.Chatterjee (Georgia Tech)
4.3	Wavelet Analysis of Measurements for On-Line Testing Analog & Mixed-Signal Circuits M.Dimopoulos, A.Spyronasios, A.Hatzopoulos (Alexander Techn. Educational Inst. of Thessaloniki, Aristotle U. of Thessaloniki)

4:15 PM - 4:30 PM COFFEE BREAK

4:30 PM - 5:30 PM	Session 5 - System-Level Dependability
5.1	A framework to support the design of COTS-based reliable space computers for on-board data handling S.Campagna, M.Violante (Politecnico di Torino)
5.2	Checkpointing Virtual Machines Against Transient Errors L.Wang, Z.Kalbarczyk, R.Iyer, A.Iyengar (University of Illinois at Urbana Champaign and IBM Research)
5.3	Qualification and Relifing Testing for Space Applications Applied to the Agilent G-Link Components M.Pignol, F.Malou, C.Aicardi (CNES)

5:30 PM - 5:45 PM BREAK

5:45 PM - 7:15 PM	Special Session 1 – Panel: SER standards: Where we are? What's next? Organizers/Moderators: E.Ibe (Hitachi), M.Nicolaidis (TIMA Lab)
	Participants: D.Alexandrescu (iRoC) R.Baumann (TI) A.Bougerol (EADS) E.Ibe (Hitachi) S.Rezgui (Actel) C.Slayman (Ops A La Carte)

8:00 PM WELCOME RECEPTION

July 6, 2010 (Tuesday)

9:00 AM - 10:00 AM	Session 6 - Fault Tolerance in 3D ICs and FPGAs
6.1	Configurable Serial Fault-Tolerant Link for Communication in 3D Integrated Systems V.Pasca, L.Anghel, C.Rusu, M.Benabdenbi (TIMA Lab)
6.2	RILM: Reconfigurable Inter-Layer Routing Mechanism for 3D Multi-Layer Networks-on-Chip C.Rusu, L.Anghel, D.Avresky (TIMA Lab, IRIANC)
6.3	An FPGA-based Fail-soft System with Adaptive Reconfiguration R.Noji, S.Fujie, Y.Yoshikawa, H.Ichihara, T.Inoue (Hiroshima City U.)

10:00 AM - 10:15 AM BREAK

10:15 AM - 11:15 AM	Special Session 2 –Advances in Reliable Analog/RF Circuits Organizers/Moderators: H.Stratigopoulos (TIMA Lab), Y.Makris (Yale U.)

11:15 AM - 11:30 AM COFFEE BREAK

11:30 AM - 12:50 PM	Session 7 - Memory Test, Repair, and Fault Tolerance Chair: First Last (Affiliation)
7.1	Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories S.Bota, G.Torrens, B.Alorda, J.Verd, J.Segura (U. des Illes Ballears)
7.2	Programmable Restricted SEC Codes for Hard Errors in Semiconductor Memories S.Evain, Y.Bonhomme, V.Gherman (CEA, LIST)
7.3	A Bit Level Area Aware Cache-Based Architecture for Memory Repairs N.Axelos (National Technical U. Athens), K.Pekmestzi (National Technical U. Athens)
7.4	A Software-Based Self-Test Methodology for In-System Testing of Processor Cache Tag Arrays G.Theodorou, N.Kranitis, A.Paschalis, D.Gizopoulos (U. Athens and U. Piraeus)

12:50 PM - 2:00 PM LUNCH

2:00 PM - 3:00 PM	Session 8 - On-Line Testing Techniques
8.1	An on-line fault detection technique based on embedded debug features M.Grosso, M.Sonza Reorda, M.Portela-Garcia, M.Garcia Valderas, C.Lopez-Ongil, Luis Entrena (Politecnico di Torino and U. Carlos III de Madrid)
8.2	A Partitioning Approach to Improve Reconfigurable Neuron-inspired Online BIST A.Shahabi, S. Behdad Hosseini, H.Sohofi, Z.Navabi (U. Tehran and Worcester Polytechnic Institute)
8.3	Selecting State Variables for Improved On-Line Testability Through Output Response Comparison of Identical Circuits I.Pomeranz (Purdue U.), S.Reddy (U. Iowa)

3:00 PM - 4:00 PM	Session 9 - Posters
9.1	A Method for Detecting Resistive Opens in Buses J.RIUS (UPC)
9.2	A new framework for the automatic insertion of mitigation structures in circuits netlists N.Battezzati, D.Serrone, M.Violante (Politecnico di Torino)
9.3	Application Dependent FPGA Testing Using The ASIC Test Methods and Tools M.Rozkovec, J.Jenicek, O.Novak (Technical U. Liberec)
9.4	Fully Distributed Initialization Procedure for a 2D-Mesh NoC, Including Off Line BIST and Partial Deactivation of Faulty Components Z.Zhang, A.Greiner, M.Benabdenbi (U. Pierre et Marie Curie & LIP6-SoC, TIMA Laboratory,Grenoble INP-UJF-CNRS, Grenoble University)
9.5	Improving Fault Handling Software Techniques P.Gawkowski, T.Rutkowski (Warsaw U. Technology)
9.6	Investigating the Use of BICS to Detect Resistive-Open Defects in SRAMs R.Chipana, L.Veiras Bolzani, Fabian Vargas, A.Calimera, E.Macii, J.Semiao, J.Rodriguez-Andina, I.Teixeira, J.P.Teixeira (Catholic University – PUCRS, Politecnico di Torino, U. Algarve, U. Vigo, INESC)
9.7	New Self-Checking Arithmetic Logic Unit with Duplicated Outputs V.Ocheretny (Fraunhofer SIT)
9.8	Online fault testing of reversible logic using dual rail coding N.Farazmand, M.Zamani, M.Tahoori (Northeastern U. and Karlsruhe Institute of Technology)
9.9	Reconfigurable Low-Power Concurrent Error Detection in Logic Circuits S.Almukhaizim, S.Bunian, O.Sinanoglu (Yale U. and Kuwait U.)
9.10	Robust Cryptographic Ciphers with On-line Statistical Properties Validation A.Vaskova, C.Lopez-Ongil, A.Jimenez-Horas, E.San Millan, Luis Entrena (U. Carlos III of Madrid)
9.11	Trustworthy Computing in a Multi-Core System Using Distributed Scheduling D.McIntyre, F.Wolff, C.Papachristou, S.Bhunia (Cleveland State U. and Case Western Reserve U.)

4:30 PM SOCIAL EVENT (Tour and Gala Dinner)

July 7, 2010 (Wednesday)

9:00 AM - 9:45 AM	Keynote Talk II Michael Orshansky, Professor, U. Texas at Austin

9:45 AM - 10:00 AM BREAK

10:00 AM - 11:00 AM	Special Session 3 – Reliability and Test in 3D ICs Organizer: R.Aitken (ARM)

11:00 AM - 11:15 AM COFFEE BREAK

11:15 AM - 12:35 PM	Session 10 - Secure Systems Chair: First Last (Affiliation)
10.1	Evaluation of Concurrent error detection techniques on the Advanced Encryption Standard K.Bousselam, G.Di Natale, M.-L.Flottes, B.Rouzeyre (LIRMM)
10.2	Message authentication mechanism secure against power analysis attacks P.Duplys, E.Boehl, W.Rosenstiel (Robert Bosch GmbH and U. Tubingen)
10.3	Study of Single-Bit Fault Injection Techniques by Laser on an AES Cryptosystem A.-P.Mirbaha, J.-M.Dutertre, A.Tria, M.Agoyan, A.-L.Ribotta, D.Naccache (ENSMSE-CMP, CEA-LETI, Ecole Normale Supérieure)
10.4	Robust FSMs for Cryptographic Devices Resilient to Strong Fault Injection Attacks Z.Wang, M.Karpovsky (Boston U.)

12:35 PM - 1:30 PM LUNCH

1:30 PM - 2:50 PM	Session 11 - On-Line Error Detection and Fault Tolerance
11.1	On-Line Detection of Random Voltage Perturbations In Buses With Multiple-Threshold Receivers M.Skoufis (Raytheon), S.Tragoudas (Southern Illinois U.)
11.2	Design of Embedded Constant Weight Code Checkers Based on Averaging Operations S.Tarnick (FBE-ASIC GmbH)
11.3	On-line Testing of Bundled-Data Asynchronous Handshake Protocols S.Zeidler, A.Bystrov, M.Krstic, R.Kraemer (IHP GmbH and U. Newcastle Upon Tyne)
11.4	Reducing the area overhead of TMR-systems by protecting specific signals M.Augustin, M.Goessel, R.Kraemer (BTU Cottbus, U. Potsdam, and IHP GmbH)

2:50 PM - 3:00 PM BREAK

3:00 PM - 4:00 PM	Session 12 - Soft and Timing Error Tolerance
12.1	Robust Detection of Soft Errors Using Delayed Capture Methodology P.V, V.Singh, R.Parekhji (Texas Instruments India and Indian Institute of Science)
12.2	Timing Error Tolerance in Nanometer ICs S.Valadimas (U. Athens), Y.Tsiatouhas (U. Ioannina), A.Arapoyanni (U. Athens)
12.3	Error Resilient Video Encoding Using Block-Frame Checksums J.Wells, J.Natarajan, A.Chatterjee, I.Barlas (Georgia Tech. and Impact Technologies)

4:00 PM - 4:15 PM	Symposium Closing Remarks

More Information

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General Information

Michael Nicolaidis
TIMA Laboratory
Grenoble, France
Tel: +33 (0) 4 76 57 46 96
Michael.Nicolaidis@imag.fr

Antonis Paschalis
University of Athens
Dept. of Informatics & Telecomm.
Athens, Greece
Tel: +30 210 727 5231
paschali@di.uoa.gr

Committees

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General Chairs
M. Nicolaidis, TIMA Laboratory
A. Paschalis, U. Athens

Vice-General Chairs
X. Vera, Intel Labs Barcelona
Y. Zorian, Virage Logic

Program Chairs
D. Gizopoulos, U. Piraeus
A. Chatterjee, Georgia Tech.

Vice-Program Chairs
M. Abadir, Freescale
S. Chakravarty, LSI Logic

Special Sessions
R. Aitken, ARM
Y. Makris, Yale U.

Finance Chair
N. Kranitis, U. Athens

Local Arrangements
A. Merentitis, U. Athens
G. Theodorou, U. Athens

Audio Visual Chair
N. Foutris, U. Piraeus
V. Dimitsas, U. Piraeus

Publications
M. Psarakis, U. Piraeus
N. Zergainoh, TIMA Laboratory

ETTTC Liaison
M. Sonza Reorda, Politec. di Torino

Publicity
L. Anghel, TIMA Laboratory
R. Velazco, TIMA Laboratory

Program Committee
J. Abraham, U. Texas at Austin
D. Alexandrescu, iRoC
D. Appello, ST Microelectronics
M. Baklashov, ARM
R. Baumann, TI
M. Benabdenbi, LIP6
N. Bidokhti, Cisco
E. Boehl, Robert Bosch GmbH
N. Buard, EADS
A. Bystrov, U. Newcastle
Y. Cao, Arizona State U.
V. Chandra, ARM
J. Collet, LAAS
G. Di Natale, LIRMM
R. Drechsler, U. Bremen
P. Fouillat, IXL-ENSEIRB
G. Georgakos, Infineon
P. Girard, LIRMM
M. Goessel, U. Postdam
W. Gustin, Infineon
A. Haggag, Freescale
J. Hayes, U. Michigan
T. Heijmen, NXP
S. Hellebrand, U. Paderborn
E. Ibe, Hitachi
A. Ivanov, U. Brit. Columbia
R. Iyer, U. Illinois
A. Krasniewski, Warsaw U.T.
R. Kumar, U. Illinois
S. Kundu, U. Mass. Amherst
R. Leveugle, TIMA
A. Majumdar, AMD/ATI
C. Metra, U. Bologna
M. Miranda, IMEC
S. Mitra, Stanford U.
F. Monteiro, U. Metz
S. Mukhopadhyaya, Georgia Tech.
D. Nikolos, U. Patras
P. Pande, Washington State U.
C. Papachristou, CWRU
R. Parekhji, TI
B. Paul, Toshiba
Z. Peng, Linkoping U.
S. Piestrak, U. Metz
M. Pignol, CNES
I. Polian, U. Freiburg
D. Pradhan, U. Bristol
P. Prinetto, Politec. di Torino
H. Puchner, Cypress
M. Rebaudengo, Politec. di Torino
K. Roy, Purdue U.
M. Santos, INESC-ID
J. Segura, U. Illes Balears
N. Seifert, Intel
E. Simeu, TIMA Laboratory
A. Singh, Auburn U.
C. Slayman, Sun
H. Stratigopoulos, TIMA
J.-P. Teixeira, IST/INESC-ID
N. Touba, U. Texas
S. Tragoudas, U. Southern Illinois
T. Uemura, Fujitsu Labs
F. Vargas, PUCRS
M. Violante, Politec. di Torino
I. Voyiatzis, TEI Athens
L.-C. Wang, U. C. Santa Barbara
H. J. Wunderlich, U. Stuttgart
Q. Xu, Chinese U. Hong Kong

For more information, visit us on the web at: http://tima.imag.fr/conferences/iolts

The 16th IEEE International On-Line Testing Symposium (IOLTS2010) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).